1. Field of the Invention
The present invention generally relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device including a reference cell which is compared with a selected memory cell in read operation.
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a non-volatile memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the use of thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells significantly improves performance of the MRAM device. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000, and xe2x80x9cA 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAMxe2x80x9d, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 18 schematically shows the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 18, the MTJ memory cell includes a tunneling magneto-resistance element TMR and an access transistor ATR. Tunneling magneto-resistance element TMR has an electric resistance varying according to a magnetically written storage data level. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between a bit line BL and a source voltage line SL. Typically, a field effect transistor formed on a semiconductor substrate is used as access transistor ATR.
A bit line BL, a write digit line WDL, a word line WL and a source voltage line SL are provided for the MTJ memory cell. Bit line BL and write digit line WDL allow data write currents of different directions to flow therethrough in write operation, respectively. Word line WL is used to conduct read operation. Source voltage line SL pulls down tunneling magneto-resistance element TMR to a ground voltage GND in read operation. In read operation, tunneling magneto-resistance element TMR is electrically coupled between source voltage line SL and bit line BL in response to turning-ON of access transistor ATR.
FIG. 19 is a conceptual diagram illustrating write operation to the MTJ memory cell.
Referring to FIG. 19, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL having a fixed magnetization direction (hereinafter, sometimes simply referred to as xe2x80x9cfixed magnetic layerxe2x80x9d), and a ferromagnetic material layer VL that is magnetized in the direction corresponding to an external magnetic field (hereinafter, sometimes simply referred to as xe2x80x9cfree magnetic layerxe2x80x9d). A tunneling barrier (tunneling film) TB is interposed between fixed magnetic layer FL and free magnetic layer VL. Tunneling barrier TB is formed from an insulator film. Free magnetic layer VL is magnetized either in the same direction as or in the opposite direction to that of fixed magnetic layer FL according to a write data level. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
The electric resistance of tunneling magneto-resistance element TMR varies according to the relation between the respective magnetization directions of fixed magnetic layer FL and free magnetic layer VL. More specifically, the electric resistance of tunneling magneto-resistance element TMR has a minimum value Rmin when fixed magnetic layer FL and free magnetic layer VL have the same (parallel) magnetization direction, and has a maximum value Rmax when they have opposite (antiparallel) magnetization directions.
In write operation, word line WL is inactivated and access transistor ATR is turned OFF. In this state, a data write current for magnetizing free magnetic layer VL is applied to each of bit line BL and write digit line WDL in a direction corresponding to the write data level.
FIG. 20 is a conceptual diagram showing the relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in write operation.
Referring to FIG. 20, the abscissa H(EA) indicates a magnetic field which is applied to free magnetic layer VL of tunneling magneto-resistance element TMR in the easy-axis (EA) direction. The ordinate H(HA) indicates a magnetic field which is applied to free magnetic layer VL in the hard-axis (HA) direction. Magnetic fields H(EA), H(HA) respectively correspond to two magnetic fields produced by the currents flowing through bit line BL and write digit line WDL.
In the MTJ memory cell, fixed magnetic layer FL is magnetized in the fixed direction along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized either in the direction parallel or antiparallel (opposite) to that of fixed magnetic layer FL along the easy axis according to the storage data level (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d). The MTJ memory cell is thus capable of storing 1-bit data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) according to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when the sum of the applied magnetic fields H(EA) and H(HA) reaches the region outside the asteroid characteristic line in FIG. 20. In other words, the magnetization direction. of free magnetic layer VL does not change if the strength of an applied data write magnetic field corresponds to the region inside the asteroid characteristic line.
As shown by the asteroid characteristic line, applying a magnetic field of the hard-axis direction to free magnetic layer VL enables reduction in a magnetization threshold value required to change the magnetization direction along the easy axis.
When the operation point of write operation is designed as in the example of FIG. 20, a data write magnetic field of the easy-axis direction is designed to have a strength HWR in the MTJ memory cell to be written. In other words, a data write current to be applied to bit line BL or write digit line WDL is designed to produce the data write magnetic field HWR. In general, data write magnetic field HWR is given by the sum of a switching magnetic field HSW required to switch the magnetization direction and a margin xcex94H. Data write magnetic field HWR is thus given by HWR=HSW+xcex94H.
In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of a prescribed level or more must be applied to both write digit line WDL and bit line BL. Free magnetic layer VL in tunneling magneto-resistance element TMR is thus magnetized in the direction parallel or opposite (antiparallel) to that of fixed magnetic layer FL according to the direction of the data write magnetic field along the easy axis (EA). The magnetization direction written to tunneling magneto-resistance element TMR, i.e., the storage data of the MTJ memory cell, is held in a non-volatile manner until another data write operation is conducted
FIG. 21 is a conceptual diagram illustrating read operation from the MTJ memory cell.
Referring to FIG. 21, in read operation, access transistor ATR is turned ON in response to activation of word line WL. As a result, tunneling magneto-resistance element TMR is pulled down to ground voltage GND and electrically coupled to bit line BL.
If bit line BL is then pulled up to a prescribed voltage, a memory cell current Icell corresponding to the electric resistance of tunneling magneto-resistance element TMR, that is, the storage data level of the MTJ memory cell, flows through a current path including bit line BL and tunneling magneto-resistance element TMR. For example, the storage data can be read from the MTJ memory cell by comparing memory cell current Icell with a prescribed reference current.
The electric resistance of tunneling magneto-resistance element TMR thus varies according to the magnetization direction that is rewritable by an applied data write magnetic field. Accordingly, non-volatile data storage can be realized by using electric resistances Rmax, Rmin of tunneling magneto-resistance element TMR as the storage data levels (xe2x80x9c1xe2x80x9dand xe2x80x9c0xe2x80x9d).
Data storage of the MRAM device is thus realized by using the difference between connection resistances, xcex94Rcell (xcex94Rcell=Rmaxxe2x88x92Rmin), which corresponds to the difference between storage data levels in tunneling magneto-resistance element TMR.
In general, the MRAM device includes reference cells in addition to normal MTJ memory cells for storing data. In read operation, a reference cell is compared with a memory cell selected for read operation (hereinafter, sometimes referred to as xe2x80x9cselected memory cellxe2x80x9d). In such an MRAM device, the storage data level of the selected memory cell is determined by comparing the access result to the selected memory cell with the access result to the reference cell.
For example, a reference cell is designed so that a current passing therethrough has an intermediate value of two memory cell currents Icell corresponding to the two electric resistances Rmax, Rmin of the MTJ memory cell. In this case, a reference cell must be fabricated to have an electric resistance having an intermediate level of electric resistances Rmax, Rmin. However, implementation of such an electric resistance requires special design and fabrication for a reference cell. This complicates the reference cell structure, thereby possibly causing an increased chip area and a reduced processing margin of a memory cell array.
In a common MTJ memory cell, the resistance difference xcex94Rcell generated according to the storage data level is not so large. Typically, electric resistance Rmin is at most about several tens of percents of electric resistance Rmax. Memory cell current Icell therefore varies at most on the order of microamperes (xcexcA: 10xe2x88x926A) according to the storage data level. A reference cell is therefore required to generate a reference current with high accuracy. Accordingly, it must be ensured that erroneous reading occurs if characteristics of a reference cell are varied in a manufacturing process.
Moreover, a reference cell is commonly provided for every plurality of MTJ memory cells. Therefore, the reference cell is accessed more frequently than each MTJ memory cell. Such frequent access to the reference cell degrades the characteristics of the reference cell with time, thereby possibly reducing read operation accuracy.
Such a problem occurs not only in an MRAM device but also in a non-volatile semiconductor memory device which conducts read operation based on the access result to a selected memory cell and a reference cell. Therefore, read operation accuracy of such a non-volatile semiconductor memory device must be prevented from being reduced even if the characteristics of a reference cell are varied in a manufacturing process or degraded with time.
It is an object of the present invention to provide a non-volatile semiconductor memory device capable of stably conducting read operation even if characteristics of a reference cell are varied in a manufacturing process or degraded with time.
According to one aspect of the present invention, a non-volatile semiconductor memory device includes a plurality of memory cells, a reference cell, a spare reference cell, a reference cell selecting section, and a data read circuit. Each of the plurality of memory cells stores data in a non-volatile manner. The reference cell is compared with a selected one of the plurality of memory cells in read operation. The spare reference cell has same characteristics as those of the reference cell, and is provided as a spare of the reference cell. The reference cell selecting section selects one of the reference cell and the spare reference cell in the read operation. The data read circuit reads storage data of the selected memory cell based on access to the one of the reference cell and the spare reference cell which is selected by the reference cell selecting section and access to the selected memory cell. The reference cell selecting section is capable of switching selection of the reference cell and the spare reference cell according to conditions.
Accordingly, a main advantage of the present invention is that selection of the reference cell and the spare reference cell is not fixed before the non-volatile semiconductor memory device is used, but can be dynamically switched according to various conditions after the non-volatile semiconductor memory device is used. Therefore, read operation accuracy can be retained even if characteristics of the reference cell are varied in the manufacturing process or degraded with time. As a result, operation reliability can be improved.
According to another aspect of the present invention, a non-volatile semiconductor memory device includes a plurality of memory cells, a plurality of reference cells, and a data read circuit. Each of the plurality of memory cells stores data in a non-volatile manner. The plurality of reference cells are compared with a selected one of the plurality of memory cells in read operation. The data read circuit reads storage data of the selected memory cell based on access to the selected memory cell and access to at least two of the plurality of reference cells in the read operation.
The above non-volatile semiconductor memory device conducts read operation from the selected memory cell based on access to a plurality of reference cells. Therefore, even if at least-one of the plurality of accessed reference cells have unsatisfactory characteristics, the influence of such unsatisfactory characteristics is reduced, whereby possibility of erroneous reading can be suppressed. As a result, operation reliability can be improved in terms of manufacturing variation of reference cell characteristics and degradation in reference cell characteristics with time.
According to still another aspect of the present invention, a non-volatile semiconductor memory device includes a plurality of memory cells, a reference cell, a data read circuit, and a reference cell test section. Each of the plurality of memory cells stores data in a non-volatile manner. The reference cell is compared with a selected one of the plurality of memory cells in read operation. The data read circuit reads storage data of the selected memory cell based on access to the reference cell and access to the selected memory cell in the read operation in normal operation. The reference cell test section tests the reference cell in operation test other than the normal operation.
Since the reference cell is more frequently accessed than the memory cells, the reference cell is more likely to be degraded with time. The above non-volatile semiconductor memory device is capable of conducting operation test for detecting a defective reference cell even after the non-volatile semiconductor memory device is used.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.